(or equivalent authorised by Director of Studies)
Aims: To acquire an appreciation of the suitability of different techniques for the analysis of and representations for programming languages, followed by the various means to interpret them. To demonstrate the impact that computer architecture is having on compiler design. To explore trends in hardware development, and examine techniques for efficient use of machine resources.
Learning Outcomes:
1.To be able to choose suitable techniques for lexing, parsing, type analysis, intermediate representation, transformation and interpretation given the properties of the language to be implemented.
2.To be able to describe the philosophy of RISC and CISC architectures.
3.Knowledge of at least one technique for register allocation, and one technique for instruction scheduling.
4.The ability to write a simple code generator.
Skills:
Problem solving (T/F, A).
Content:
Construction of lexical analysers, recursive descent parsing, construction of LR parser tables, type checking, polymorphic type synthesis, abstract interpretation, storage management, byte-code interpreters, code-threaded interpreters, partial evaluation, staging transformations.Description of several state-of-the-art chip designs. The implications for compilers of RISC architectures. Register allocation algorithms (colouring, DAGS, scheduling). Global data-flow analysis. Pipelines and instruction scheduling; delayed branches and loads. Multiple instruction issue. VLIW and the Bulldog compiler. Harvard architecture and Caches. Benchmarking.
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