Department of Electronic and Electrical Engineering
 
Dr Chris Clarke of the Department of Electronic and Electrical Engineering (EEE)

Contact details

Room 2 East 2.9a

Tel: +44 (0) 1225 386993

Email: C.T.Clarke@bath.ac.uk

 

Dr Christopher T Clarke

PBEng, PhD

Profile

Dr Clarke received a BEng degree in Engineering Electronics and a PhD degree in Computer Science from the University of Warwick in 1989 and 1994 respectively.

From 1994 to 1997 Dr Clarke lectured at Nanyang Technological University in Singapore where he was a cofounder of the Centre for High Performance Embedded Systems (CHiPES).

Since then he has spent time in industry, both as an in-house engineering manager and independent consultant for UK silicon design houses, system integrators and multinationals such as Philips Semiconductors.

Dr Clarke joined the Microelectronics and Optoelectronics research group in the Department of Electronic and Electrical Engineering at the University of Bath in March 2003. He has been involved with many bio-medical and bio-mimetic European Union-funded research projects including CIRCE (IST-2001-35144), SENS, and IMANE.

Dr Clarke is a member of the Centre for Advanced Sensor Technologies (CAST) and has published in excess of 30 papers in conferences and journals. He is the Director of Studies for postgraduate taught courses.

Research

Dr Clarke’s research is centred on IC design and Signal Processing. He has been actively involved in a number of EU projects (SENS, CIRCE, PEPS, IMANE), and EPSRC projects. These projects and other research in collaboration with post-graduate students has included the creation of:

  • A 20Mgate design that was the first biologically plausible scale real time biomimetic model of the auditory system of a bat. This was used for robotic navigation in realistic outdoor environments using ultra-sound. This system was implemented on a pair of Xilinx Virtex2 FPGAs
  • A prototype implantable nerve signal sensor device using multichannel dipole receivers and 4 level digital signaling to detect nerve signal impulses in a real world environment.
  • An architecture for the correction of barrel distortion in images in real time.
  • A low complexity Filter Cache architecture with low area, high performance whilst retaining the power savings available in more complex filter cache structures.
  • An architecture for block compression of software with hard or soft decompressors

Publications

Book Sections

Lam, S. K., Srikanthan, T. and Clarke, C.T., 2012. Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration. In: ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings. IEEE.

Prakash, A., Lam, S.-K., Clarke, C. T. and Srikanthan, T., 2011. Instruction set customization for area-constrained FPGA designs. In: Proceedings - IEEE International SOC Conference, SOCC 2011. Piscataway, NJ: IEEE Computer Society, pp. 329-334. (International System on Chip Conference)

Kwan, P. C. and Clarke, C. T., 2005. FPGAs for improved energy efficiency in processor based systems. In: Advances in Computer Systems Architecture.Vol. 3740. Berlin: Springer, pp. 440-449. (Lecture Notes in Computer Science)

Clarke, C. T., Qiang, L., Peremans, H. and Hernandez, A., 2004. FPGA implementation of a neuromimetic cochlea for a bionic bat head. In: Field Programmable Logic and Application.Vol. 3203. Berlin: Springer, pp. 1073-1075. (Lecture Notes in Computer Science)

Clarke, C. T. and Nudd, G. R., 1994. Redundant Arithmetic CORDIC System with a Unit Scale Factor. In: McWirter, J. G., ed. Mathematics in Signal Processing III. Oxford: Oxford University Press, pp. 63-73.

Articles

Casado, C., Timmers, R., Sergejevs, A., Clarke, C. T., Allsopp, D. W. E., Bowen, C. R., van Grieken, R. and Marugán, J., 2017. Forthcoming. Design and validation of a LED-based high intensity photocatalytic reactor for quantifying activity measurements. Chemical Engineering Journal, 327, pp. 1043-1055.

Metcalfe, B., Clarke, C., Donaldson, N. and Taylor, J., 2017. A New Method for Neural Spike Alignment: The Centroid Filter. IEEE Transactions on Neural Systems and Rehabilitation Engineering

Clarke, C., Rieger, R., Schuettler, M., Donaldson, N. and Taylor, J., 2017. An Implantable ENG Detector with In-System Velocity Selective Recording (VSR) Capability. Medical and Biological Engineering and Computing, 55 (6), pp. 885-895.

Metcalfe, B. W., Chew, D. J., Clarke, C. T., Donaldson, N. d. N. and Taylor, J. T., 2015. A new method for spike extraction using velocity selective recording demonstrated with physiological ENG in Rat. Journal of Neuroscience Methods, 251, pp. 47-55.

Lam, S. K., Srikanthan, T. and Clarke, C. T., 2014. Rapid evaluation of custom instruction selection approaches with FPGA estimation. ACM Transactions on Embedded Computing Systems, 13 (4), 75.

Lam, S.-K., Clarke, C.T. and Srikanthan, T., 2014. Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration. ACM Transactions on Reconfigurable Technology and Systems, 7 (3), 26.

Betts, D., Bowen, C.R., Kim, H.A., Gathercole, N., Clarke, C.T. and Inman, D.J., 2013. Nonlinear dynamics of a bistable piezoelectric-composite energy harvester for broadband application. European Physical Journal - Special Topics, 222 (7), pp. 1553-1562.

Prakash, A., Lam, S.-K., Clarke, C.T. and Srikanthan, T., 2013. FPGA-aware techniques for rapid generation of profitable custom instructions. Microprocessors and Microsystems, 37 (3), pp. 259-269.

Betts, D.N., Bowen, C.R., Kim, H.A., Gathercole, N., Clarke, C.T. and Inman, D.J., 2013. Investigation of bistable piezo-composite plates for broadband energy harvesting. Proceedings of SPIE, 8688, 86881N.

Al-Shueli, A., Clarke, C. T., Donaldson, N. and Taylor, J. T., 2013. Improved signal processing methods for velocity selective neural recording using multi-electrode cuffs. IEEE Transactions on Biomedical Circuits and Systems, 8 (3), pp. 401-410.

Taylor, J., Schuettler, M., Clarke, C. T. and Donaldson, N., 2012. The theory of velocity selective neural recording: a study based on simulation. Medical and Biological Engineering and Computing, 50 (3), pp. 309-318.

Lam, S. K., Srikanthan, T. and Clarke, C. T., 2011. Architecture-aware technique for mapping area-time efficient custom instructions onto FPGAs. IEEE Transactions on Computers, 60 (5), pp. 680-692.

Lam, S. K., Srikanthan, T. and Clarke, C. T., 2009. Selecting profitable custom instructions for area-time-efficient realization on reconfigurable architectures. IEEE Transactions on Industrial Electronics, 56 (10), pp. 3998-4005.

Clarke, C. T., Xu, X., Rieger, R., Taylor, J. and Donaldson, N., 2009. An implanted system for multi-site nerve cuff-based ENG recording using velocity selectivity. Analog Integrated Circuits and Signal Processing, 58 (2), pp. 91-104.

Suchitra, S., Lam, S. K., Clarke, C. T. and Srikanthan, T., 2006. Accelerating rotation of high-resolution images. IEE Proceedings - Vision Image and Signal Processing, 153 (6), pp. 815-824.

Lam, S. K., Srikanthan, T. and Clarke, C. T., 2006. Rapid generation of custom instructions using predefined dataflow structures. Microprocessors and Microsystems, 30 (6), pp. 355-366.

Rieger, R., Schuettler, M., Pal, D., Clarke, C., Langlois, P., Taylor, J. and Donaldson, N., 2006. Very low-noise ENG amplifier system using CMOS technology. IEEE Transactions on Neural Systems and Rehabilitation Engineering, 14 (4), pp. 427-437.

Vivekanandarajah, K., Srikanthan, T., Clarke, C. T. and Bhattacharyya, S., 2004. A novel static prediction scheme for filter cache structures. IEICE Transactions on Electronics, E87C (4), pp. 543-548.

Qiang, L. and Clarke, C., 2004. Digital neuromorphic processing for a simplified algorithm of ultrasonic reception. The Journal of the Acoustical Society of America (JASA), 115 (5), p. 2518.

Srikanthan, T., Bhardwaj, M. and Clarke, C. T., 1998. Area-time-efficient VLSI residue-to-binary converters. IEE Proceedings - Computers and Digital Techniques, 145 (3), pp. 229-235.

Conference or Workshop Items

Sergejevs, A., Clarke, C., Allsopp, D., Marugan, J. and Bowen, C., 2016. A calibrated UV LED light source for photocatalytic experimentation. In: ASEAN-EU STI Days, 2016-05-10 - 2016-05-12, 44B Ly Thuong Kiet Street.

Beasley, A., Walker, L. and Clarke, C., 2015. Developing and Implementing Dynamic Partial Reconfiguration for Pre-Emptible Context Switching and Continuous End-To-End Dataflow Applications. In: Altera SoC Developers Forum, 2015-10-14 - 2015-10-14, steigenberger airport hotel.

Taylor, J., Metcalfe, B., Clarke, C., Chew, D., Nielsen, T. and Donaldson, N., 2015. A Summary of Current and New Methods in Velocity Selective Recording (VSR) of Electroneurogram (ENG). In: 2015 IEEE International Symposium on VLSI, 2015-07-07 - 2015-07-10, Frane.

Beasley, A., 2014. The Implications of Second Order Effects of Practical Components on Storing Energy Harvested by Pyro-electric and Piezo-electric Effects. In: Clarke, C., Bowen, C. and Zabek, D. A., eds. nanosmat, 2014-09-08 - 2014-09-11, Trinity College.

Metcalfe, B., Chew, D., Clarke, C., Donaldson, N. and Taylor, J., 2014. An enhancement to velocity selective discrimination of neural recordings:extraction of neuronal firing rates. In: 2014 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2014-08-26 - 2014-08-30.

Metcalfe, B., Chew, D., Clarke, C., Donaldson, N. and Taylor, J., 2014. Fibre-selective discrimination of physiological ENG using velocity selective recording: Report on pilot rat experiments. In: 2014 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2014-08-26 - 2014-08-30.

Wong, L. C. C., Jolly, P., Clarke, C. T. and Estrela, P., 2014. Enhanced label-free DNA hybridisation detection using Open Circuit Potential measurement with gold nanoparticles. In: 24th Anniversary World Congress on Biosensors, 2014-05-27 - 2014-05-30.

Wong, L. C. C., Clarke, C. and Estrela, P., 2013. Label-free biosensor arrays using open circuit potential measurements. In: 3rd International Conference on Bio-Sensing Technology, 2013-05-11 - 2013-05-14.

Prakash, A., Lam, S.-K., Srikanthan, T. and Clarke, C. T., 2013. Modelling communication overhead for accessing local memories in hardware accelerators. In: 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, 2013-06-05 - 2013-06-07. IEEE, pp. 31-34.

Prakash, A., Srikanthan, T. and Clarke, C.T., 2012. Custom instructions with local memory elements without expensive DMA transfers. In: 22nd International Conference on Field Programmable Logic and Applications, 2012-08-28 - 2012-08-30. IEEE, pp. 647-650.

Wang, D., Clarke, C.T. and Evans, A., 2012. Examination of the concept of a row-column separated median filter. In: 22nd International Conference on Field Programmable Logic and Applications, 2012-08-28 - 2012-08-30. IEEE, pp. 659-662.

Rieger, R., Taylor, J. and Clarke, C., 2012. Signal processing for velocity selective recording systems using analogue delay lines. In: 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012, 2012-05-20 - 2012-05-23.

Al-Shueli, A., Clarke, C. T. and Taylor, J. T., 2012. Simulated nerve signal generation for multi-electrode cuff system testing. In: 2012 International Conference on Biomedical Engineering and Biotechnology (iCBEB), 2012-05-28 - 2012-05-30.

Taylor, J., Schuettler, M., Clarke, C. and Donaldson, N., 2011. A summary of the theory of velocity selective neural recording. In: 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS 2011, 2011-08-30 - 2011-09-03.

Clarke, C. T., Taylor, J. T. and Xu, X., 2008. Analogue/digital interface and communications aspects in a multi-channel ENG recording asic. In: IEEE International Symposium on Circuits and Systems (ISCAS 2008), 2008-05-18 - 2008-05-21.

Taylor, J. and Clarke, C., 2008. Improved harmonic analysis of RC-active phase shift oscillators. In: IEEE International Symposium on Circuits and Systems (ISCAS 2008), 2008-05-18 - 2008-05-21.

Xu, X. H., Clarke, C. T. and Taylor, J. T., 2008. Multi-site nerve cuff based implantable system for wide bandwidth ENG signal recording. In: 2nd International Conference on Signal Processing and Communication Systems (ICSPCS 2008), 2008-12-15 - 2008-12-17.

Sathyanarayana, S., Srikanthan, T. and Clarke, C. T., 2007. Real Time Tracking of Camera Motion through Cylindrical Passages. In: 15th International Conference on Digital Signal Processing, 2007-07-01 - 2007-07-04.

Vivekanandarajah, K., Srikanthan, T. and Clarke, C. T., 2006. Profile directed instruction cache tuning for embedded systems. In: IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, 2006-03-02 - 2006-03-03.

Durga, P. and Clarke, C., 2006. System-On-Chessboard: A rapid SOC implementation. In: 2006 IASTED Conference on Advances in Computer Science and Technology, 2006-01-23 - 2006-01-25.

Rieger, R., Taylor, J., Clarke, C., Pal, D., Langlois, P. and Donaldson, N., 2005. 10-channel very low-noise ENG amplifier system using CMOS technology. In: IEEE International Symposium on Circuits and Systems (ISCAS 2005), 2005-05-23 - 2005-05-26.

Clarke, C., Taylor, J., Rieger, R. and Donaldson, N., 2005. A distributed neural sensor system. In: IEEE International Symposium on Circuits and Systems (ISCAS 2005), 2005-05-23 - 2005-05-26.

Clarke, C., Taylor, J., Rieger, R. and Donaldson, N., 2005. A distributed neural signal sensor system. In: IEEE International Symposium on Circuits and Systems (ISCAS 2005), 2005-05-23 - 2005-05-26.

Suchitra, S., Sneha, S., Srikanthan, T. and Clarke, C., 2005. Elimination of sign precomputation in flat CORDIC. In: IEEE International Symposium on Circuits and Systems (ISCAS 2005), 2005-05-23 - 2005-05-26.

Lam, S., Srikanthan, T., Clarke, C. and Low, H., 2004. Achieving hardware-efficient neural network based pattern recognition system through linear approximation. In: 38th Asilomar Conference on Signals, Systems and Computers, 2004-11-07 - 2004-11-10.

Clarke, C., Qiang, L., Peremans, H. and Muller, R., 2004. An FPGA based bio-mimetic implementation of neural signal processing in bats. In: IoA Symposium on Bio-sonar Systems & Bio-Acoustics, 2004-09-14 - 2004-09-16.

Clarke, C. T. and Qiang, L., 2004. Bat on an FPGA: a biomimetic implementation of a highly parallel signal processing system. In: 38th Asilomar Conference on Signals, Systems and Computers, 2004-11-07 - 2004-11-10.

Xu, X., Clarke, C. and Jones, S., 2004. High performance code compression architecture for the embedded ARM/THUMB processo. In: Computing Frontiers, 2004-04-14 - 2004-04-16.

Clarke, C. T. and Srikanthan, T., 2004. Residue arithmetic techniques for hardware reduction in pseudo-random sequence correlators. In: 38th Asilomar Conference on Signals, Systems and Computers, 2004-11-07 - 2004-11-10.

Xu, X. H., Jones, S. R. and Clarke, C. T., 2003. ARM/THUMB code compression for embedded systems. In: 15th International Conference on Microelectronics (ICM 2003), 2003-12-09 - 2003-12-11.

Vivekanandarajah, K., Srikanthan, T., Clarke, C. T. and Bhattacharyya, S., 2003. Static pattern predictor (SPP) based low power instruction cache design. In: International Conference on Embedded Systems and Applications (ESA03), 2003-06-23 - 2003-06-26.

Bhardwaj, M., Srikanthan, T. and Clarke, C. T., 1999. A reverse converter for the 4-moduli superset {2n-1, 2 n, 2n+1, 2n+1+1}. In: 14th IEEE Symposium on Computer Arithmetic, 1999-04-14 - 1999-04-16.

Bhardwaj, M., Srikanthan, T. and Clarke, C. T., 1999. VSLI costs of arithmetic parallelism: A residue reverse conversion perspective. In: 14th IEEE Symposium on Computer Arithmetic, 1999-04-14 - 1999-04-16.

Srikanthan, T., Gisuthan, B. and Clarke, C. T., 1998. A Framework for Computing scaling factors for Flat CORDIC. In: Symposium on High Performance Computing (HPC), 1998-10-23 - 1998-10-25.

Deodhar, A. A., Bhurdwaj, M., Clarke, C. T. and Srikanthan, T., 1998. Designing efficient residue arithmetic based VLSI correlators. In: IEEE International Conference on Acoustics, Speech and Signal Processing, 1998-03-12 - 1998-03-15.

Srikanthan, T., Bhardwaj, M. and Clarke, C. T., 1997. Implementing area-time efficient VLSI residue to binary converters. In: IEEE Workshop on Signal Processing Systems - Design and Implementation (SIPS 97), 1997-11-05.

Srikanthan, T., Clarke, C. T., Lam, S. K. and Wee, L. C., 1997. Auto-Generator for FPGA-XILINX To VLSI-MAGIC Conversion. In: 7th International Symposium on IC Technology, Systems and Applications (ISIC-97), 1997-09-10 - 1997-09-12.

Clarke, C. T. and Nudd, G. R., 1995. Highly Non-Linear Encoders For Current Mode Multiple-Valued Logic. In: 6th International Symposium on IC Technology, Systems & Applications (ISIC-95), 1995-09-06 - 1995-09-08.

Clarke, C. T. and Nudd, G. R., 1995. Shallow Multiplication Circuits in VLSI. In: 6th International Symposium on IC Technology, Systems & Applications (ISIC-95), 1995-09-06 - 1995-09-08.

Clarke, C. T. and Nudd, G. R., 1995. Three Dimensional CORDIC with Reduced Iteration. In: 6th International Symposium on IC Technology, Systems & Applications (ISIC-95), 1995-09-06 - 1995-09-08.

Clarke, C. T., 1995. Unraveling CORDIC. In: 6th International Symposium on IC Technology, Systems & Applications (ISIC-95), 1995-09-06 - 1995-09-08.

Clarke, C. T., Nudd, G. R. and Summerfield, S., 1994. Current mode techniques for multiple valued arithmetic and logic. In: IEEE International Symposium on Circuits and Systems (ISCAS '94), 1994-05-30 - 1994-06-02.

Nudd, G. R., Papefstathiou, E., Papay, Y., Atherton, T. J., Clarke, C. T., Kerbyson, D. J., Stratton, A. F., Ziani, R. and Zemerly, M. J., 1993. A Layered Approach to the Characterisation of Parallel Systems for Performance Prediction. In: Performance Evaluation of Parallel Systems (PEPS'93), 1993-11-01.

Nudd, G. R., Atherton, T. J., Kerbyson, D. J., Clarke, C. T., Papay, Y., Papaefstathiou, E., Ziani, R. and Zemerly, J., 1993. Assessing the Performance of Parallel Computers - PEPS (ESPRIT 6942). In: 2nd Workshop on Abstract Machine Models for Highly Parallel Computers, 1993-04-01.

Summerfield, S., Clarke, C. T. and Nudd, G. R., 1992. VLSI arithmetic with current mode multiple valued logic. In: IEEE International Symposium on Circuits and Systems (ISCAS '92), 1992-05-10 - 1992-05-13.

Thesis

Clarke, C. T., 1993. The Implementation and Applications of Multiple-Valued Logic. Thesis (Doctor of Philosophy (PhD)). University of Warwick.

Patent

Plans Casal, D., Clarke, C., Leonard, P., Dei, A. and Morelli, D., 2016. Device and method for providing feedback on breathing rate. US 9,610,017 B2, 13 October 2016.

Clarke, C., 2006. A Method and Apparatus For Correlating Data Sequences. G01S1/00- WO2006048676 (A1), 11 May 2006.

This list was generated on Sat Oct 21 09:19:18 2017 IST.